The present invention relates generally to graphics processors and, more particularly, to a lighting module of a graphics pipeline system.
Prior Art FIG. 1 illustrates a general system that implements a pipelined graphics processing system. In this system, data source 10 generates a stream of expanded vertices defining primitives. These vertices are passed one at a time, through pipelined graphic system 12 via vertex memory 13 for storage purposes. Once the expanded vertices are received from the vertex memory 13 into the graphics pipeline system 12, the vertices are transformed and lit by a transformation module 14 and a lighting module 16, respectively, and further clipped and set-up for being rendered by a rasterizer 18, thus generating rendered primitives that are then displayed on display device 20.
During operation, the lighting module 16 is responsible for lighting vertices according to various lighting parameters. The lighting parameters may include, for example, a stack of the current lights along with their associated parameters, the ambient light level, and a material. The various lighting and shading models as well as various other parameters of the lights themselves may determine how a vertex should he lit, as is well known in the art.
In the past, there have been many attempts to design hardware implementations of the various components of the standard graphics-processing pipeline including the lighting module. Such designs have primarily focused on increasing speed, efficiency, and an overall performance of the processing architecture.
A method and apparatus are provided for a lighting system for graphics processing. Included is a plurality of input buffers adapted for being coupled to a transform system for receiving vertex data therefrom. The input buffers include a first input buffer, a second input buffer and a third input buffer. An input of the first buffer, the second input buffer and the third input buffer are coupled to an output of the transform system.
Further included is a multiplication logic unit having a first input coupled to an output of the first input buffer and a second input coupled to an output of the second input buffer. An arithmetic logic unit has a first input coupled to an output of the second input buffer. The arithmetic logic unit further has a second input coupled to an output of the multiplication logic unit. An output of the arithmetic logic unit is coupled to the output of the lighting system.
Next provided is a first register unit having an input coupled to the output of the arithmetic logic unit and an output coupled to the first input of the arithmetic logic unit. A second resister unit has an input coupled to the output of the arithmetic logic unit. Also, such second register has an output coupled to the first input and the second input of the multiplication logic unit.
A lighting logic unit is also provided having a first input coupled to the output of the arithmetic logic unit, a second input coupled to the output of the first input buffer, and an output coupled to the first input of the multiplication logic unit.
In one embodiment, the lighting logic unit is capable of flagging to allow the vertex data to modify vertex processing. First, the vertex data is processed in the lighting logic unit in accordance with a plurality of mode bits which are indicative of a status of a plurality of modes of process operations, and subsequently outputted. Thereafter, at least one flag is set upon the vertex data satisfying predetermined criteria. This flag may then be used for the purpose of performing if/then/else clamping to 0.0 in the lighting, equations at no performance penalty. Another use of the foregoing flag register may be in setting a write mask for register writes.
Further, memory is coupled to at least one of the inputs of the multiplication logic unit and the output of the arithmetic logic unit. The memory has stored therein a plurality of constants and variables for being used in conjunction with the input buffers, the multiplication logic unit, the arithmetic logic unit, the first register unit, the second register unit and the lighting logic unit for processing the vertex data.
These and other advantages of the present invention will become apparent upon reading the following detailed description and studying the various figures of the drawings.